The present invention relates to a data capture logic system to be used with very large scale integrated circuit chips, also known as VLSI chips, to provide test and error checking functions in addition to the operational functions of the chip. More particularly, the present invention relates to a data capture logic system which may be located on the VLSI chip and programmed to store certain operands from the VLSI logic function during operation, as well as storing operands at different time cycles during operation so that the functioning of the circuit may be analyzed. This invention has particular application to VLSI chips that have a pipeline or pipe sequence of operations.
The increasing complexity of logic design as implemented on VLSI chips has created problems with respect to the fact that large amounts of the circuitry contained within a single VLSI array cannot be directly sampled or tested. With very large arrays, a substantial number of logic or functional steps can occur between input operands and output operands so that if some types of error are present in the output operand, it is difficult to determine where or in what manner the error came about. The ability to test or otherwise determine the functioning of a logic circuit in a VLSI array is especially important during the design check-out process so that internal logic can be sampled to verify the logic design, as well as to identify "weak" areas in the array design or layout which might be especially sensitive to error development during the life of a VLSI chip. Such "weak" areas may have poor tolerance or margins to voltage fluctuation, timing variations or other factors. Therefore, it is important in VLSI logic design to create an internal system which can test or sample preselected, important data points internal to the logic structure. Because some errors are intermittent and do not occur under all conditions, but only under certain conditions, it is especially difficult to diagnose these errors in large systems. Diagnosis of intermittent errors can be especially aided if the failing input data at various positions internal to a logic circuit can be captured along with the input operands to the logic structure. Similarly, because input and output connections or pins to VLSI logic chip arrays are limited in number and primarily used for operational purposes, tests for error function logic must be allowed to take only a very small number of the input and output pins that can be placed on a VLSI chip.
Error checking and test logic is extremely important in VLSI design and, consequently, there is a substantial amount of prior art directed to this problem.
One known technique for analyzing VLSI logic design and error functions is known as the level sensitive scan design in which a substantial number of registers are combined with the logic system on a VLSI chip so that on demand the contents of all of the registers may be delivered in a continuous serial fashion to an output pin of the chip. This system requires the stringing together of a significant number of operand registers in the VLSI chip in order to output a substantial body of serial data. All of this data is captured at the same time and represents a burden to analyze all of the particular operands and unnecessary information captured by this method. Also, this method does not capture the correct input operands to correlate with operands in various processing steps.
Another method of VLSI chip design is represented by U.S. Pat. No. 4,233,682, which shows that a fault detection and isolation system can be designed using a substantial amount of duplicate logic in the system design combined with comparators at various stages of processing. As long as the comparators show that the processing steps are producing identical operands, then no error output is indicated. However, when the operands at a particular point in the logic function are not identical, then an error output is indicated and the correct operand is selected for output if it is possible to determine which operand is correct. This system creates the burden in logic design of duplicating all essential functions of the logic together with comparator logic for comparing the operands at various stages of processing. This design and the comparator logic will penalize the speed performance of the circuit. While this duplication of logic may be necessary in some applications, it should not be necessary for all applications. Also, this duplicate logic system may show that an error is occurring internal to a logic system, but does not help determine the type of error that is occurring by capturing both input and failing output operands from the same internal function.
A forerunner of the present data capture logic system is shown and described in U.S. Pat. No. 4,357,703 owned by the same assignee as the present invention. That patent showed that certain test functions could be performed with LSI logic and that input and output operands could be captured in parallel fashion in registers for serial shifting into and out of the chip for test purposes. This system was good for LSI level logic design but VLSI demands other techniques because of the high logic density on a chip. Moreover, that patent does not show a system for capturing data operands internally in the VLSI logic structure at different times during functioning of the VLSI logic.